1. Field of the Invention
The invention relates to a method of wafer-scale integration that is suitable for different wafer sizes and to a new device structure that can be realized with this method.
2. Description of the Related Art
In semiconductor technology a three-dimensional integration of different materials, fabricated with different process technologies and with different functionality (e.g. sensor/CMOS, memory/processor), may raise difficulties when the available wafer sizes of the desired process technologies do not match (e. g. 200 mm CMOS with 100 mm compound semiconductor wafers; or 300 mm digital processor with 200 mm analog circuits). Furthermore, yield losses may be increased by methods of wafer-scale integration, because it is not possible to select dies at wafer-scale (“known good die” filtering, KGD).
Methods of placing or bonding semiconductor dies onto carrier wafers are described in US 2007/285115 A1, US 2008/265407 A1, US 2009/178275 A1, and US 2010/144068 A1, for example.
DE 10 2008 048 303 B3 and WO 2009/072056 A2 describe methods of integration of CMOS circuits with direct x-ray conversion materials. These methods use solder joints or wire-bonds to make the necessary connections.
U.S. Pat. No. 7,227,150 B2 describes a conventional method of applying a bias voltage to a cathode contact by wire bonding.